Since at least the 1960's bipolar transistors have been used for high speed integrated circuits such as in emitter coupled logic (ECL) circuits. A typical (basic) emitter coupled logic circuit consists of a pair of n-p-n transistors with the collectors coupled to separate first and second load resistors and the emitters coupled to a resistor or to the collector of a third n-p-n transistor whose emitter is coupled to a third resistor. Such a circuit can exhibit rise and fall times in the pico-second range. One problem with this circuit is that power dissipation is higher than is desired in some applications. One partial solution to the power dissipation problem is to stack emitter coupled pairs of n-p-n transistors on top of each other to form a tree type configuration. It is known to have two levels of emitter coupled pairs of transistors with an n-p-n transistor coupled by the collector thereof to the emitters of one of the levels. This substantially increases the amount of logic which can be used while maintaining speed and power at the same level as is used with a single pair of emitter coupled transistors. Thus the speed/power product of the resulting tree configuration is significantly improved as compared to the basic emitter coupled configuration.
One limitation on the tree configuration of emitter coupled logic circuits is that in order to operate at very high speeds, the transistors must be operated out of saturation in what is known as the linear range of operation. This requires that the voltage across the collector-emitter regions of the transistors of each level be about one volt. Typical output voltage signal levels of emitter coupled circuits have magnitude of about 0.7 volts. In addition, voltage across the constant current source which comprises the third transistor and the third resistor is typically about 2 volts or more. Accordingly, a power supply voltage of about 5 volts is needed for proper operation. The supply voltage can not be lowered much because of the need to keep the transistors out of saturation so as to insure very high speed operation. Accordingly, power dissipation is still higher than is desired in some applications.
BI-FETS use a combination of field effect and bipolar transistors. The field effect transistor's high input impedance characteristic makes it useful as an input device. The low output impedance of the bipolar transistor makes it useful as an output device.
SRAMs exist which use a mixture of bipolar and field effect transistors. A bipolar-CMOS static random access memory which includes a sense amplifier having a pair of emitter coupled n-p-n transistors and a field effect transistor (FET) is disclosed in U.S. Pat. No. 4,825,413 (H. V. Tran). The emitters of the transistors are coupled to the drain of the FET whose source is connected to a reference potential. The FET is described as being turned on to provide a current path for the transistors. Variations in the characteristics of the FET, such as gate oxide thickness, and in the voltage level applied to the gate thereof can cause variations in the current flow through the FET. This makes this type of configuration less than ideal for use in applications in which a constant current source is desired.
Some logic applications which require constant current sources use a multi-level tree type configuation which requires multiple logic and voltage levels as inputs. The above described configuration of U.S. Pat. No. 4,825,413 is not useful in these applications.
In applications such as logic circuits, which are standardized and are known as master slice or library circuits, typically only standard logic levels are used and it becomes a problem to use multiple different voltage logic levels typically required by bipolar and field effect transistors.
It is desirable to have ECL type logic circuits which have very high speed operation with lower power dissipation than conventional ECL circuits.